1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and, more specifically, to a method of thinning a silicon body of a silicon-on-insulator (SOI) substrate.
2. Discussion of Related Art
Gordon Moore originally suggested in 1964 that the pace of technology innovation would result in the doubling of the number of transistors per unit area on an IC chip every 12 months. By 1975, the trend had changed to a doubling every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to Moore's Law in improving the density for every generation of devices. Maintaining such an aggressive schedule has required the scaling down of the transistors in complementary metal oxide semiconductor (CMOS) circuits by using steeper retrograde wells, triple wells, more abrupt source/drain (S/D) junctions, thinner gate dielectric layer, shorter channel length, and more highly-doped channels.
However, doping the channel to a concentration higher than about 1018 atoms/cm3 degrades carrier mobility and junction characteristics. Tunneling of electrons through the gate dielectric layer also becomes a problem when the thickness of the gate dielectric layer is about 1.5 nanometers (nm) or less. Consequently, beginning with the 90-nm technology node and continuing through the 65-nm technology node, the scaling of planar metal-oxide-semiconductor field effect transistors (MOSFETs) that are fabricated in a bulk silicon substrate has become increasingly hampered by short-channel effects (SCE), such as leakage and threshold voltage, Vt, stability.
Thus, even more drastic changes have been required in the device structure and the manufacturing process in order to address SCE. One significant change is substrate enhancement, such as silicon-on-insulator (SOI) technology. An SOI device is a device that is formed in a thin layer of semiconducting material, such as a silicon body, located over a layer of insulating material, such as an oxide, that is embedded in a substrate, such as a silicon wafer.
SOI can lower parasitic capacitance and reduce substrate leakage thereby enabling faster switching speeds and lower-voltage operation. A device built in SOI has a higher drive current, Ion, and a lower off-state leakage current, Ioff compared with a device built in bulk silicon. Lowering the threshold voltage allows the thickness of the SOI to be reduced. Reducing the SOI thickness allows much better control over SCE. Threshold voltage, Vt, also becomes more consistent for devices with varying channel lengths of 0.6 micron (um) and below.
An SOI device is considered to be partially-depleted when the depletion region in the channel below the gate electrode does not extend completely through the thickness of the silicon body. However, the performance advantage of a partially-depleted SOI device over a bulk-silicon device diminishes when the dimensions are scaled down. A partially-depleted SOI device is also subject to a floating body effect (FBE) which may increase the complexity of the design of the IC.
An SOI device is considered to be fully-depleted when the depletion region in the channel below the gate electrode extends all the way through the thickness of the silicon body. A device built in SOI will be fully-depleted across a range of operating conditions when the thickness of the silicon body is about 40 nm or less. A fully-depleted SOI device has a shorter channel length and displays a more ideal transistor function, such as very sharp turn-on characteristics.
A chemical-mechanical polish (CMP) process may be used to reduce the thickness of the silicon body for an SOI device. However, the thickness of the silicon body may become very non-uniform due to fluctuations in polish pressure or slurry distribution, especially when the SOI device is fabricated in a large substrate, such as a 300-millimeter diameter wafer.
A process alternating between oxidation and etch may be used to reduce the thickness of the silicon body for an SOI device. However, many cycles are required to remove a large amount of silicon.
Thus, what is needed is a method of thinning a silicon body of an SOI substrate.